tel-netlist-reader

name: tel-netlist-reader description: Parse and analyze .tel PCB netlist files to extract hardware connectivity (nets, pins, component interconnects, and fanout). Use when a user provides a .tel netlist, asks for hardware connection relationships, wants pin/net tracing, or needs a structured summary (JSON/table) from legacy netlist text.

TEL Netlist Reader

Overview

Use this skill to read .tel netlist files and convert them into structured connectivity data for PCB hardware analysis.

Prefer running the bundled parser script first, then answer circuit-connection questions from the parsed JSON.

Workflow

1. Parse .tel file with the script in scripts/parse_tel_netlist.py.
2. Inspect summary, nets, and component_to_nets in JSON output.
3. Answer user questions such as:

• which components are on a net
• which nets a component pin connects to
• high-fanout rails (for example GND, VDD33)

Commands

From any directory:

python C:/Users/ckdfs/.codex/skills/tel-netlist-reader/scripts/parse_tel_netlist.py <path/to/file.tel>

Custom output path:

python C:/Users/ckdfs/.codex/skills/tel-netlist-reader/scripts/parse_tel_netlist.py <path/to/file.tel> --output <path/to/out.json>

Interpretation Rules

• Read $PACKAGES as component/package metadata and reference designator groups.
• Read $NETS as logical nets with node lists in RefDes.Pin format.
• Handle multiline net entries (continuation lines after commas).
• Strip optional single quotes around net names.
• Preserve Chinese text and symbols when possible; if terminal display is garbled, trust UTF-8 JSON output.

Output Expectations

Return concise hardware-centric findings:

• power nets and attached devices
• MCU pins and external headers/connectors
• named signal paths (for example SWDIO, SWCLK, NRST)
• suspicious single-node or unexpectedly large-fanout nets

For detailed format caveats and examples, see references/tel-format-notes.md.