Explore AI Agent Skills & Claude Prompts

Use when generating chip module diagrams (block diagrams, timing diagrams, FSM diagrams). Triggers on '框图', '时序图', '状态机图', 'diagram', '架构图', '画图', '画一个'. Generates module block diagrams, timing diagrams and state machine diagrams. Primary format: D2→PNG for block/FSM diagrams, Wavedrom→PNG for timing diagrams.

chip-png-interface-gen

Use when generating interface port PNG diagrams from Verilog module declarations. Triggers on '接口图', '端口图', 'interface gen', 'port diagram', '接口PNG', 'module snapshot'. Generates module_snapshot style port PNGs with inputs on left, outputs on right, signal names with width and direction arrows.

vf-pipeline

Use this skill to start or resume the VeriFlow RTL hardware design pipeline (architect to synth). Trigger this when the user asks to "run the RTL flow", "design hardware", or "start the pipeline". Pass the project directory path as the argument.

schedule Updated 2 months ago

chip-doc-structurer

Use when designing microarchitecture document structure. Triggers on '文档结构', '章节设计', 'doc structure', '文档模板', '内容权重', '文档组织'. Designs chapter structure and content weight allocation for microarchitecture specifications.

chip-impl-input-triage

Use when checking RTL implementation input completeness before coding. Triggers on '输入确认', 'input triage', '输入检查', '文档完整性', '输入分类', 'input check'. Checks microarch docs, coding style, CBB list completeness and selects execution path.

chip-impl-module-structure

Use when planning RTL module structure from microarchitecture docs. Triggers on '模块结构', '端口列表', '子模块划分', '文件清单', 'module structure', 'port list'. Extracts ports, submodule partitioning and file list from microarch docs.

chip-impl-quality-gate

Use when running lint checks, synthesis, or quality gates on RTL code. Triggers on '综合', 'lint', 'synth', 'quality gate', '质量门禁', '门禁', 'verilator', 'yosys', '自检', 'check'. Executes lint+synth checks with auto-heal loop on failures.

chip-impl-self-check

Use when performing final self-check on RTL implementation before delivery. Triggers on '自检', 'self-check', 'self check', '实现自检', 'quality checklist', 'IC-01', 'IM-01', '检查清单'. Runs IC-01~39 + IM-01~08 implementation quality checklist.

chip-interface-contractor

Use when defining module interface contracts. Triggers on '接口契约', 'interface contract', '信号列表', '接口定义', '端口定义', '接口时序'. Defines signal list, timing, protocol behavior and SVA for module interfaces.

chip-png-d2-gen

Use when generating D2 architecture diagrams, data flow diagrams, or FSM state machine diagrams. Triggers on 'd2', '架构图', '框图', '状态机图', 'diagram', '数据通路图', 'generate d2', '模块连接图'. Compiles .d2 source to PNG using dagre layout.

chip-png-wavedrom-gen

Use when generating Wavedrom timing diagrams as PNG images. Triggers on '时序图', 'wavedrom', 'timing diagram', '波形图', '时序分析图', 'generate wavedrom'. Compiles Wavedrom JSON to PNG using wavedrom-cli.

chip-ppa-formatter

Use when formatting PPA specification tables. Triggers on 'PPA表', 'PPA格式', 'ppa formatter', '面积表', '功耗表', '性能表', 'PPA规格'. Outputs structured PPA specs with unit normalization and constraint expressions.