Explore AI Agent Skills & Claude Prompts

Interactive wizard to craft effective prompts using Claude Code best practices

schedule Updated 14 days ago

pqc-readiness

Use when assessing a system's readiness for post-quantum cryptography migration, inventorying classical crypto usage, mapping NIST-standardized PQC replacements, and planning phased migration timelines. Covers key exchange, digital signatures, and hybrid mode needs. Do not use for classical crypto implementation review (use crypto-review) or protocol state machine analysis (use protocol-analysis).

formal-spec

Use when writing formal specifications in TLA+ to verify system properties, defining state variables, configuring TLC model checker, and documenting assumptions and limitations. Covers safety and liveness properties for protocols and concurrent systems. Do not use for security claim enumeration without specification intent (use invariant-analysis).

soc-integration

Use when planning SoC integration including bus fabric architecture, memory map allocation, IP qualification, interrupt routing, and design-for-test strategy. Covers AMBA/AXI protocols, register map design, DFT insertion, and production test planning. Do not use for RTL design flow (use chip-design-flow) or block-level verification (use verification-methodology).

embedded-architecture

Use when designing firmware architecture for embedded or IoT devices. Covers RTOS selection, memory layout, power state machine, task decomposition, and watchdog recovery design. Do not use for wireless protocol selection (use protocol-design) or fleet-scale device management (use fleet-management).

protocol-design

Use when selecting and designing communication protocol stacks for IoT or embedded systems. Covers physical layer selection, transport and application protocols, security layers, message format design, and error resilience. Do not use for firmware architecture (use embedded-architecture) or fleet-scale operations (use fleet-management).

caching-strategy

Use when designing or auditing a caching architecture. Covers multi-layer cache hierarchy, key schema, TTL policies, invalidation flows, and warming strategies. Do not use for runtime performance profiling (use performance-audit) or capacity planning (use load-modeling).

kernel-hardening

Use when auditing kernel security configuration for memory protection, syscall surface reduction, control flow integrity, and integrity mechanisms against local and remote attack vectors. Covers CIS/KSPP benchmarks, KASLR, SMAP/SMEP, seccomp, and secure boot chain. Do not use for isolation boundary analysis (use isolation-review) or HW/SW interface review (use hw-sw-boundary).

a11y-audit

Use when auditing accessibility compliance of a feature or codebase. Covers WCAG 2.2 AA conformance, screen reader compatibility, keyboard navigation, focus management, color contrast, reduced motion, and ARIA usage. Do not use for general UX review (use journey-mapping) or component interaction specs (use interaction-design).

cost-analysis

Use when modeling infrastructure costs, projecting scaling expenses, or identifying optimization opportunities across cloud providers and third-party services. Covers per-unit cost estimation, growth milestone projections, and budget alerting setup. Do not use for deployment strategy design (use deployment-plan) or monitoring architecture (use observability-design).

hw-security-signoff

Use when a hardware design needs security sign-off before tape-out. Defines the builder-to-auditor handoff contract between Foundry (constructive design) and Forge (security review). Covers security review prerequisites, artifact checklist, sign-off criteria, and conditional approval workflow. Do not use for RTL security review itself (use rtl-security-review) or design flow guidance (use foundry/chip-design-flow).

chip-design-flow

Use when guiding RTL-to-GDSII chip design flow including RTL coding style, synthesis constraints, place-and-route strategy, timing closure, and tape-out checklist. Do not use for verification methodology (use verification-methodology) or SoC integration (use soc-integration).